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At the heart of an inverter is the IGBT, a costly power device which must switch extremely fast and is required to withstand the high DC bus voltage. The efficiency and reliability provided by these power devices are of utmost importance to maximize the performance of the inverter.
Optocouplers are commonly used in inverters to provide safe galvanic isolation between the control circuits and to help protect against damage caused by high voltages in the DC bus. In particular, gate drive optocouplers are widely used to drive IGBTs since they can provide high output current for precise switching and fault detection features for IGBT protection.
The ACPL-339J is the industry’s first dual-output gate drive optocoupler, uniquely designed to support a MOSFET buffer to maximizes gate drive design scalability and power conversion efficiency. It also offers a compact and cost-effective solution for protecting the IGBT with integrated features like UVLO, short circuit detection and “soft” IGBT turn-off.
Attendees will learn:
- How to drive IGBT for better power conversion efficiency
- How to protect IGBT to improve system overall reliability
- The advantages ACPL-339J and achieving system design scalability, efficiency and reliability
Mobile communications, network servers, multimedia, and consumer SoCs must achieve the highest processor performance while consuming the minimal amount of energy. Logic libraries with a wide variety of high-performance flip-flops, clock tree cells and combinational cells provide an efficient method for optimizing CPU and GPU performance. Synopsys’ multi-VT/multi-channel logic libraries and datapath libraries take advantage of high-performance, processor-optimized EDA tool flows, and enable SoC designers to achieve gigahertz performance within the constraints of aggressive power budgets.
In this webinar you will learn:
- Ways to maximize system performance while managing power budgets of CPU, GPU, and other SoC blocks, each with different performance/power/area targets
- How combining innovative power management techniques using multiple VTs/channel lengths in different SoC logic blocks delivers the optimal tradeoff in SoC watts per gigahertz